a16z · Oct 9, 2026 · 54m · 35m saved
With Pat Gelsinger, General Partner at Playground Global, previously CEO of Intel and of VMware
Pat Gelsinger expects AI data center projects to start defaulting because the electricity to run them will not be there.
Most of the AI hardware debate is about whose chip is fastest. Gelsinger said AI tools have already made chip design the easy part, and that the hard limits are now in factories, packaging, memory and power.
"Whenever you have the technology to make something easy, that means the bottleneck moves somewhere else." — Pat Gelsinger
Pat Gelsinger, General Partner at Playground Global, on a16z, joined Intel as an 18-year-old technician, was engineer number four on the 386 and architect of the 486, and later ran VMware and then Intel as chief executive. At Playground he invests in the companies trying to fix the bottlenecks he describes here.
The full interview is covered here so you can skip it. 54 minutes of audio, 19 minutes of reading.
Here are the 14 predictions that matter.
Key Takeaways
Designing a chip with AI takes about three months; getting it into use takes nine more
Fab time, 3D packaging and rack integration each add roughly three months
The roughly 100 AI chip startups will consolidate to a few
High-bandwidth memory wastes power, heat and space, and chip designers lose about 40% of their power budget to safety margins
New memory technologies are coming for the first time in 30 years, because the memory makers are finally profitable
Chip stacks will stop at three to five layers, because every extra layer multiplies the yield problem
Copper connections inside AI racks give way to optics around 2028–29
US energy capacity was flat for 10 to 15 years, and Gelsinger treats energy capacity as economic capacity
New gas turbines take eight years to arrive
Nvidia's power per teraflop has not improved in five generations, so he is backing new physics such as superconducting chips
Every piece of VMware's management layer has to be rebuilt for AI agents
1. Intel Hired Him at 18
One host opened by comparing a new a16z program for talented 16- to 22-year-olds with Gelsinger's own route into the industry: a trade school, then straight into Intel.
He skipped the end of high school and was recruited by Intel before he had ever flown
"I'm 16 years old, I accidentally win a scholarship, I go to tech school, right, skipped my last year and a half of high school, and Intel comes recruiting when I'm 18 years old." — Pat Gelsinger
He had never been on an airplane. His interviewer, Ron Smith, saw him 12th that day and wrote "Smart, aggressive, arrogant, he'll fit right in." Gelsinger started as a technician, moved onto the design team at the end of the 286, was engineer number four on the 386 and became architect and design manager for the 486, while studying for his bachelor's, master's and PhD.
At Stanford he argued with his professors using what he was building at Intel
A Stanford professor proposed a new carry-look-ahead adder design, a circuit that speeds up binary addition, for a book he was about to publish. Gelsinger tried it on the 386, found it did not work, and spent the next two class periods arguing with him about why. He had similar arguments with Ed McCluskey, the father of built-in self-test, a way for a chip to check itself, saying most of his ideas were not practical for real chips even as Gelsinger was putting self-test to work on the 386.
"John Hennessy was my thesis advisor, and obviously he did okay — I say I helped his career, he became president, and he's done okay since then." — Pat Gelsinger
The hosts said that friction between professors and students who work in industry is part of what makes Silicon Valley unusual.
